Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. In current industry practice, verification by simulation, or dynamic verification, is the leading technique for functional verification. Coverage is used to ensure that the verification of the design is thorough, and the definition of “coverage events” or testing requirements is a major part in the definition of the verification plan of the design. Often, a family of coverage events that share common properties are grouped together to form a “coverage model”. Members of the coverage model are called “coverage tasks” and are considered part of the coverage model. These models are defined by a basic event and a set of parameters or attributes, where the list of coverage tasks comprises all permissible combinations of values for the attributes.
Reference is now made to FIG. 1, which illustrates the verification process with an automatic random test generator 10. A coverage model 12 is translated by a verification team 14 to a set of directives 16 for the random test generator 10. Based on these directives 16 and embedded domain knowledge, test generator 10 produces many test-cases 18. A simulator 20 then simulates a design under test (DUT) 22 using generated test-cases 18 and the behavior of DUT 22 is monitored using checking (e.g. “assertion”) tools and other checking methods, such as final results comparisons, to make sure that it meets its specification. In addition, coverage tools 24 are used to review the coverage information 25 produced by simulator 20 and to detect the occurrence of coverage tasks during simulation. Analysis of reports 26 allows verification team 14 to modify directives 16 to test generator 10 to overcome weaknesses in the implementation of coverage model 12. This process is repeated until the exit criteria in coverage model 12 are met.
The use of automatic test generators can dramatically reduce the amount of manual labor required to implement coverage model 12. Even so, the manual work needed for analyzing the coverage reports and translating them to directives 16 for test generator 10 can constitute a bottleneck in the verification process. Therefore, considerable effort has been spent on finding ways to automate this procedure. One automated feedback process from coverage analysis to test generation is known as coverage directed test generation (CDG).
In general, the goal of CDG is to automatically provide directives that are based on coverage analysis to the test generator. This can be further divided into two sub-goals: First, to provide directives to the test generator that help in reaching hard cases, namely uncovered or rarely covered tasks. Achieving this sub-goal can shorten the time needed to fulfill the coverage model and can reduce the number of manually written directives. Second, to provide directives that allow easier reach for any coverage task, using a different set of directives when possible. Achieving this sub-goal makes the verification process more robust, because it increases the number of times a task has been covered during verification. Moreover, if a coverage task is reached via different trajectories, the chances of discovering hidden bugs related to this task are increased.
In the past, two general approaches for CDG have been proposed: feedback-based CDG and CDG by construction. Feedback-based CDG relies on feedback from the coverage analysis to automatically modify the directives to the test generator. For example, in the article, by M. Bose et al., entitled “A genetic approach to automatic bias generation for biased random instruction generation,” published in Proceedings of the 2001 Congress on Evolutionary Computation CEC2001, pages 442–448, May 2001, a genetic algorithm is used to select and modify test-cases to increase coverage. In the article by S. Tasiran, et al. entitled, “A functional validation technique: biased random simulation guided by observability-based coverage”, published in Proceedings of the 2001 International Conference on Computer Design, pages 82–88, September 2001, coverage analysis data is used to modify the parameters of a Markov Chain that represents the DUT. The Markov Chain is then used to generate test-cases for the design. In the article by G. Nativ et al. entitled “Cost evaluation of coverage directed test generation for the IBM mainframe,” published in Proceedings of the 2001 International Test Conference, pages 793–802, October 2001, the coverage analysis results trigger a set of generation rules that modify the testing directives. In contrast, in CDG by construction, an external model of the DUT is used to generate test directives designed to accurately hit the coverage tasks. For example, in the article by S. Ur and Y. Yadin entitled “Micro-architecture coverage directed generation of test programs,” published in Proceedings of the 36th Design Automation Conference, pages 175–180, June 1999, an FSM model of pipelines is used to generate tests that cover instruction interdependencies in the pipes.
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